EDGE MAJIC JTAG

As processor cores disappear inside caches, busses and other peripheral functions, the debugger connection to the processor core becomes increasingly obscured. No detailed information about processor status is available at the pins, and the JTAG role in providing access to debug logic designed into the core becomes increasingly important.

Support Tailored to Architectural Implementations

While ARM and MIPS both provide standard cores, and specify the meaning of Instruction Set compatibility, they have also accepted architectural licensees, with the ability to make changes in the core, the details of the implementation and even changes in the JTAG debug logic. While this provides certain challenges for the tools vendors, the MAJIC family uses a layered software approach to make the target core/processor support quite independent from other software tool choices.

MAJIC Firmware Supports Core Details

The details of how to set breakpoints, read and write memory, and start, stop and single step contain both common methods and core-specific details. MAJIC firmware provides modular solutions for each supported core type, providing a robust foundation for all core-specific features.

Target Boards Require Individual Attention

Targets are different for good reasons. Peripheral choices, memory mapping, memory relocation, flash memory, watchdog timers … all present a need for control during the board bring-up and BSP development process. The MAJIC software model partitions target details into a target_init.cmd file, so each unique target can have special support, independent of the processor/core and without impacting the debugger above.

Organized Flexibility

The resulting development tool environment is organized, comprehensive, flexible and easy to manage. Since the MAJIC firmware supports the full range of ARM and MIPS processor/SOC types, it is easy to move up to the next generation through standard Support Services. Fourteen standard JTAG cables complete the connection to the most popular target connector formats.

For hardware support information, visit your local distributor at www.epitools.com.

• Three tiered target support
  • Internal firmware for each core supported processor type cache management
  • Unique platform startup files
  • Target_init files for reference Platforms
• 10/100BaseT or serial comm
• Programmable JTAG clock 0 to 40 MHz
• Support for wide range of ARM & MIPS cores/processors
• OpenDebug software support multiple debug environments
• Includes memory test programs and flash programming utilities
• Three price points - range of choices
  • MAJIC-LT - low end, EDGE & GNU only
  • MAJIC-LX - complete OpenDebug s/w
  • MAJIC-MT - adds multi-core & trace upload support for Intel XScale family

• Out-of-the-box support for ~200 ARM and MIPS products
• OpenDebug™ software model provides support for multiple software development and operating system environments
• Software support is licensed to the MAJIC serial number, providing user flexibility to have multiple installations - in the office, lab, demo notebook without the restrictions of node-locked or floating license management
• Layered target control provides flexibility and comprehensive support
• Network compatibility supports shared or remote operation
• Pre-configured memory test and flash programming utilities provide support for initial board bring-up, boot code and BSP development
• Tech Support and Software/Firmware Updates available through Support Services annual renewal